1. Field of the Invention
The present invention relates to a semiconductor chip, and more particularly, to a method of forming a bonding pad on a semiconductor chip.
2. Description of the Prior Art
In a semiconductor process, when MOS transistors are formed on a semiconductor chip, the MOS transistors are connected by using multiple metallic interconnects. Contact of the metallic interconnects and the MOS transistors is avoided by depositing dielectric layers with a lower dielectric constant. This also reduces induced capacitance between them thus increasing the speed of signal transmission. When forming the last layer of metallic interconnects, a bonding pad will be formed in a predetermined area on the last dielectric layer as an interconnection area in a follow-up packaging process.
Please refer to FIG. 1. FIG. 1 is a perspective view of the structure of a bonding pad 14 of a prior art semiconductor wafer 10. After forming the last dielectric layer 12 on the semiconductor wafer 10, the last layer of metallic interconnects is formed, and a metallic layer is formed as the bonding pad 14 in a predetermined area on the dielectric layer 12. After an error-free electrical test is performed, the semiconductor wafer 10 is then sectioned into individual chips for performing a following packaging process. If the dielectric constant of the dielectric layer 12 is too high, the speed of signal transmission between the dielectric layers 12 will be reduced. Therefore, the dielectric layer 12 is made of fluoride silicate glass (FSG) in the prior art with a low dielectric constant.
Please refer to FIG. 2. FIG. 2 is a perspective view of the bonding pad 14 on a chip 15 connected to a metallic wire 18. When performing a wire bonding process, one side of the chip 15 is first fixed onto a baseplate 16 and one end of the metallic wire 18 is heated to form a metallic ball 17. This allows bonding of the metallic wire 18 to the bonding pad 14. Next, the other end of the metallic wire 18 is dragged to and linked to a predetermined area of the baseplate 16 so that electronic signals of the chip 15 can be transmitted to external components. The dielectric layer 12 below the bonding pad 14 is made of flouride silicate glass (FSG) with a lower degree of hardness. Therefore, when the metallic wire 18 is dragged across the surface of the baseplate 16, or when the chip 15 is washed by performing a supersonic vibration process, the metallic ball 17, bonding pad 14 and part of the dielectric layer 12 are peeled off from the surface of the chip 15. This causes damage to the chip 15 and reduces reliability of packaging.
It is therefore a primary objective of the present invention to provide a method of forming a bonding pad on a semiconductor chip to solve the above mentioned problem.
In a preferred embodiment, the present invention provides a method of forming a bonding pad on a semiconductor chip, the bonding pad being used to electrically connect an integrated circuit in the semiconductor chip with an external circuit, the method comprising:
forming a first dielectric layer at a predetermined area on the surface of the semiconductor chip;
forming a second dielectric layer on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer; and
forming the bonding pad on the first dielectric layer.
It is an advantage of the present invention that by using a harder first dielectric layer, the bonding pad can be firmly bonded to the surface of the semiconductor chip without peeling. Since the dielectric constant of the second dielectric layer is lower in the present invention, signal transmission speeds are not affected.
This and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.